1. Field
Exemplary embodiments of the present invention relate to a shift register circuit and a memory device including the same and, more particularly, to a technology for preventing a malfunction of a shift register circuit attributable to clock skew.
2. Description of the Related Art
A shift register circuit includes a plurality of stages, shifts a signal from a previous stage to a next stage whenever a clock is activated, and stores the shifted signal. The shift register circuit is used in almost all types of semiconductor devices. The shift register circuit may be used to delay a specific signal in synchronization with a clock and may be used to sequentially activate a plurality of signals (i.e., signals at the plurality of stages) whenever a clock is activated.
FIG. 1 illustrates the configuration of a typical shift register circuit.
Referring to FIG. 1, the shift register circuit includes flip-flops 110 and 120 that are connected in series. FIG. 1 illustrates only two stages of the shift register circuit. The shift register circuit may include tens to hundreds of stages. The flip-flops 110 and 120 may be D flip-flops (DFF).
The flip-flops 110 and 120 receive the signals of respective input terminals D, latch the received signals and output the latched signals to respective output terminals Q, at the falling edges of respective input clocks CLK1 and CLK2.
In FIG. 1, “D1” and “D2 denote paths 111 and 121 in which clocks CLK are transferred. The paths 111 and 121 may ideally have a delay value of 0, but have some delay value because it is impossible for any signal transfer path to have the delay value of 0. The input clock CLK1 is a result of the clock CLK transferred via the path 111, and the input clock CLK2 is a result of the clock CLK transferred via the path 121. In principle, the clocks CLK, CLK1, and CLK2 are the same.
FIG. 2 is a diagram illustrating an ideal operation of the shift register circuit of FIG. 1. FIG. 2 illustrates the operation of the shift register circuit if there is no skew difference (e.g., delay different) between the input clock CLK1 and the input clock CLK2.
Referring to FIG. 2, the flip-flop 110 receives its own input signal COUT<0>, latches the received input signal, and outputs the latched signal as an output signal COUT<1>, at the falling edge of the input clock CLK1. Furthermore, the flip-flop 120 receives its own input signal COUT<1> latches the received signal, and outputs the latched signal as an output signal COUT<2>, at the falling edge of the input clock CLK2.
Through the operation, the shift register circuit sequentially activates the signals COUT<1> and COUT<2> whenever the clock CLK is activated.
FIG. 3 is a diagram illustrating an erroneous operation of the shift register circuit of FIG. 1. FIG. 3 illustrates the operation of the shift register circuit if there is a skew difference between the input clock CLK1 and the input clock CLK2.
Referring to FIG. 3, the input clock CLK2 is activated later than the input clock CLK1 by a skew difference D2−D1. The flip-flop 110 receives the input signal COUT<0>, latches the received signal, and outputs the latched signal as the output signal COUT<1>, at the falling edge of the input clock CLK1. The input signal COUT<1> of the flip-flop 120 already has a “high” level at the falling edge a point of time 301) of the input clock CLK2. Accordingly, the flip-flop 120 receives the input signal COUT<1> latches the received signal, and outputs the output signal COUT<2> of a “high” level, at the falling edge (i.e., the point of time 301) of the input clock CLK2. The flip-flops 110 and 120 that form the shift register circuit are to make a difference between activation times of the respective output signals COUT<1> and COUT<2> at least by one cycle of the clock CLK. However, if an error occurs when the output signal COUT<1> of the flip-flop 110 and the output signal COUT<2> of the flip-flop 120 are activated at almost the same time, due to skew differences D2−D1 between the input clock CLK1 and the input clock CLK2.
The risk of such an error, shown in FIG. 3, is increased as the number of stages used in a shift register circuit increases and a skew between clocks used in the respective stages increases. Accordingly, there is a need for a technology capable of preventing such malfunction.